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november 2006 rev 7 1/42 1 m95040 m95020 m95010 4 kbit, 2 kbit and 1 kbit serial spi bus eeprom with high speed clock feature summary compatible with spi bus serial interface (positive clock spi modes) single supply voltage: ? 4.5 v to 5.5 v for m950x0 ? 2.5 v to 5.5 v for m950x0-w ? 1.8 v to 5.5 v for m950x0-r high speed ? 10 mhz clock rate, 5 ms write time status register byte and page write (up to 16 bytes) self-timed programming cycle adjustable size read-only eeprom area enhanced esd protection more than 1 million write cycles more than 40-year data retention packages ? ecopack? (rohs compliant) table 1. product list reference part number m95040 m95040 m95040-w m95040-r m95020 m95020 m95020-w m95020-r m95010 m95010 m95010-w m95010-r so8 (mn) 150 mil width tssop8 (dw) 169 mil width ufdfpn8 (mb) 2 3mm www.st.com
contents m95040, m95020, m95010 2/42 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 hold (hold ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 write protect (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8.3 internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8.4 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 connecting to the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.1 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.2 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.3 bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
m95040, m95020, m95010 contents 3/42 6.4 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 read from memory array (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6 write to memory array (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.7 cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 power-up and delivery states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
list of tables m95040, m95020, m95010 4/42 list of tables table 1. product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8. operating conditions (m950x0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9. operating conditions (m950x0-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 table 10. operating conditions (m950x0-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. ac test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13. dc characteristics (m950x0, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 14. dc characteristics (m950x0, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. dc characteristics (m950x0-w, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16. dc characteristics (m950x0-w, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 17. dc characteristics (m950x0-r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 18. ac characteristics (m950x0, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 19. ac characteristics (m950x0, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 20. ac characteristics (m950x0-w, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 21. ac characteristics (m950x0-w, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 22. ac characteristics (m950x0-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 23. so8n - 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 24. tssop8 ? 8 lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . 37 table 25. ufdfpn8 (mlp8) - 8-lead ultra th in fine pitch dual flat package no lead 2 3mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 26. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 27. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
m95040, m95020, m95010 list of figures 5/42 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. write enable (wren) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 8. write disable (wrdi) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9. read status register (rdsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. write status register (wrsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. read from memory array (read) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. byte write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13. page write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 14. ac test measurement i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 figure 15. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 16. hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 17. output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 18. so8n - 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 36 figure 19. tssop8 ? 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . 37 figure 20. ufdfpn8 (mlp8) - 8-lead ultra th in fine pitch dual flat package no lead 2 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
summary description m95040, m95020, m95010 6/42 1 summary description the m95040 is a 4 kbit (512 x 8) electrically erasable pr ogrammable memory (eeprom), accessed by a high speed spi-compatible bus. the other members of the family (m95020 and m95010) are identical, though proportionally smaller (2 and 1 kbit, respectively). each device is accessed by a simple serial in terface that is spi-compatible. the bus signals are c, d and q, as shown in ta b l e 2 and figure 1 . the device is selected when chip select (s ) is taken low. communications with the device can be interrupted using hold (hold ). write instructions are disabled by write protect (w ). in order to meet environmental requirements, st offers these devices in ecopack? packages. ecopack? packages are lead-free and rohs compliant. ecopack is an st trademark. ecopack specifications are available at: www.st.com . figure 1. logic diagram figure 2. 8-pin package connections 1. see section 10: package mechanical for package dimensions, and how to identify pin-1. ai01789c s v cc m95xxx hold v ss w q c d d v ss c hold q sv cc w ai01790d m95xxx 1 2 3 4 8 7 6 5
m95040, m95020, m95010 summary description 7/42 table 2. signal names c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground
signal description m95040, m95020, m95010 8/42 2 signal description during all operations, v cc must be held stable and within the specified valid range: v cc (min) to v cc (max). all of the input and output signals can be held high or low (according to voltages of v ih , v oh , v il or v ol , as specified in ta b l e 1 3 to ta bl e 1 7 ). these signals are described next. 2.1 serial data output (q) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). 2.2 serial data input (d) this input signal is used to transfer data serially into the device. it receives instructions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). 2.3 serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) ch anges after the fa lling edge of serial clock (c). 2.4 chip select (s ) when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal write cycle is in progress, the device will be in the standby power mode. driving chip select (s ) low selects the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. 2.5 hold (hold ) the hold (hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold conditio n, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be selected, with chip select (s ) driven low.
m95040, m95020, m95010 signal description 9/42 2.6 write protect (w ) this input signal is used to control whether the memory is write protected. when write protect (w ) is held low, writes to the memory are disabled, but other operations remain enabled. write protect (w ) must either be driven high or low, but must not be left floating. 2.7 v ss ground v ss is the reference for the v cc supply voltage. 2.8 supply voltage (v cc ) v cc is the supply voltage. 2.8.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see ta bl e 8 , ta bl e 9 and ta bl e 1 0 ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10nf to 100nf) close to the v cc /v ss package pins. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). 2.8.2 power-up conditions when the power supply is turned on, v cc rises from v ss to v cc . during this time, the chip select (s ) signal is not allowed to float and must follow the v cc voltage. the s line should therefore be connected to v cc via a suitable pull-up resistor. in addition, the chip select (s ) input offers a built-in safety feature, as it is both edge sensitive and level sensitive. practically this means that after power-up, the device cannot become selected until a fa lling edge has first been det ected on chip select (s ). so the chip select (s ) signal must first have been high, and then gone low before the first operation can be started. 2.8.3 internal device reset in order to prevent inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up (continuous rise of v cc ), the device will not respond to any instruction until v cc has reached the power on reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in section 9: dc and ac parameters ).
signal description m95040, m95020, m95010 10/42 when v cc has passed the por threshold voltage, the device is reset and in the following state: in standby power mode deselected (at next power-up, a falling edge is required on chip select (s ) before any instruction can be executed) not in the hold condition status register state: ? the write enable latch (wel) is reset to 0 ? the write in progress (wip) is reset to 0. the srwd, bp1 and bp0 bits of the status register are at the same logic level as when the device was last powered down (they are non-volatile bits) 2.8.4 power-down at power-down (continuous decrease of v cc ), as soon as v cc drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any inst ruction sent to it. at power-down, the device must be deselected and in standby power mode (that is there should be no internal write cycl e in progress). chip select (s ) should be allowed to follow the voltage applied on v cc .
m95040, m95020, m95010 connecting to the spi bus 11/42 3 connecting to the spi bus these devices are fully compatible with the spi protocol. all instructions, addresses and input data bytes are shifted in to the device, most significant bit first. the serial data input (d) is sampled on the first rising edge of the serial clock (c) after chip select (s ) goes low. all output data bytes are shifted out of the device, most significant bit first. the serial data output (q) is latched on the first falling edge of the serial clock (c) after the instruction (such as the read from memory array and read status register instructions) have been clocked into the device. figure 3 shows three devices, connected to an mcu, on a spi bus. only one device is selected at a time, so only one device drives the serial data output (q) line at a time, all the others being high impedance. figure 3. bus master and memory devices on the spi bus 1. the write protect (w ) and hold (hold ) signals should be driven, hi gh or low as appropriate. 2. these pull-up resistors, r, ensure that the m950x0 are not selected if the bus master leaves the s line in the high- impedance state. as the bus master may enter a state where a ll inputs/outputs are in high impedance at the same time (that is when the bus master is reset), the clock line (c) mu st be connected to an external pul l-down resistor so that, when all inputs/outputs become high impedance, s is pulled high while c is pulled low (thus ensuring that s and c do not become high at the same time, and so, that the t shch requirement is met). ai12304 bus master spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold r (2) r (2) r (2) v cc v cc v cc v cc v ss v ss v ss v ss r (2)
connecting to the spi bus m95040, m95020, m95010 12/42 3.1 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: cpol=0, cpha=0 cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from th e falling edge of serial clock (c). the difference between the two modes, as shown in figure 4 , is the clock polarity when the bus master is in stand-by mode and not transferring data: c remains at 0 for (cpol=0, cpha=0) c remains at 1 for (cpol=1, cpha=1) figure 4. spi modes supported ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
m95040, m95020, m95010 operating features 13/42 4 operating features 4.1 hold condition the hold (hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. during the hold conditio n, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to enter the hold condition, the device must be selected, with chip select (s ) low. normally, the device is kept selected, for the whole duration of the hold condition. deselecting the device while it is in the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. the hold condition starts when the hold (hold ) signal is driven low at the same time as serial clock (c) already being low (as shown in figure 5 ). the hold condition ends when the hold (hold ) signal is driven high at the same time as serial clock (c) already being low. figure 5 also shows what happens if the rising and falling edges are not timed to coincide with serial clock (c) being low. figure 5. hold condition activation 4.2 status register figure 6 shows the position of the status register in the control logic of the device. this register contains a number of control bits and status bits, as shown in ta b l e 5 . for a detailed description of the status register bits, see section 6.3: read status register (rdsr) . ai02029d hold c hold condition hold condition
operating features m95040, m95020, m95010 14/42 4.3 data protection and protocol control to help protect the device from data corruption in noisy or poorly controlled environments, a number of safety features have been built in to the device. the main security measures can be summarized as follows: the wel bit is reset at power-up. chip select (s ) must rise after the eighth clock count (or multiple thereof) in order to start a non-volatile write cycle (in the memory array or in the status register). accesses to the memory array are ignored during the non-volatile programming cycle, and the programming cycle continues unaffected. invalid chip select (s ) and hold (hold ) transitions are ignored. for any instruction to be accepted and executed, chip select (s ) must be driven high after the rising edge of serial clock (c) that latches the last bit of the instruction, and before the next rising edge of serial clock (c). for this, ?the last bit of the instruction? can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except in the case of rdsr and read instructions). moreover, the "next rising edge of clock" might (or might not) be the next bus transaction for some other device on the bus. when a write cycle is in progress, the device pr otects it against external interruption by ignoring any subsequent read, write or wrsr instruction until the present cycle is complete. table 3. write-protected block size status register bits protected block array addresses protected bp1 bp0 m95040 m95020 m95010 0 0 none none none none 0 1 upper quarter 180h - 1ffh c0h - ffh 60h - 7fh 1 0 upper half 100h - 1ffh 80h - ffh 40h - 7fh 1 1 whole memory 000h - 1ffh 00h - ffh 00h - 7fh
m95040, m95020, m95010 memory organization 15/42 5 memory organization the memory is organized as shown in figure 6 . figure 6. block diagram ai01272c hold s w control logic high voltage generator i/o shift register address register and counter data register 1 page x decoder y decoder c d q size of the read only eeprom area status register
instructions m95040, m95020, m95010 16/42 6 instructions each instruction starts with a sing le-byte code, as summarized in ta bl e 4 . if an invalid instruction is sent (one not contained in ta b l e 4 ), the device automatically deselects itself. 6.1 write enable (wren) the write enable latch (wel) bit must be set prior to each write and wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in figure 7 , to send this instruction to the device, chip select (s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be deselected, by chip select (s ) being driven high. figure 7. write enable (wren) sequence table 4. instruction set instruction description instruction format wren write enable 0000 x110 (1) 1. x = don?t care. wrdi write disable 0000 x100 (1) rdsr read status register 0000 x101 (1) wrsr write status register 0000 x001 (1) read read from memory array 0000 a 8 011 (2) 2. a8 = 1 for the upper half of the memory array of the m95040, and 0 for the lower half, and is don?t care for other devices. write write to memory array 0000 a 8 010 (2) c d ai01441d s q 2 1 34567 high impedance 0 instruction
m95040, m95020, m95010 instructions 17/42 6.2 write disable (wrdi) one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in figure 8 , to send this instruction to the device, chip select (s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be dese lected, by chip select (s ) being driven high. the write enable latch (wel) bit, in fact, becomes reset by any of the following events: power-up wrdi instruction execution wrsr instruction completion write instruction completion write protect (w ) line being held low. figure 8. write disable (wrdi) sequence c d ai03790d s q 2 1 34567 high impedance 0 instruction
instructions m95040, m95020, m95010 18/42 6.3 read status register (rdsr) one of the major uses of this instruction is to allow the mcu to poll the state of the write in progress (wip) bit. this is needed because the device will not accept further write or wrsr instructions when the previous write cycle is not yet finished. as shown in figure 9 , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte are then shifted in, on serial data input (d). the current state of the bits in the status register is shifted out, on serial data out (q). the read cycle is terminated by driving chip select (s ) high. the status register may be read at any time, even during a write cycle (whether it be to the memory area or to the status register). all bits of the status register remain valid, and can be read using the rdsr instruction. however, during the current write cycle, the values of the non-volatile bits (bp0, bp1) become frozen at a constant value. the updated value of these bits becomes available when a new rdsr instruction is executed, after completion of the write cycle. on the other hand, the two read-only bits (write enable latch (wel), write in progress (wip)) are dynamically updated during the on-going write cycle. bits b7, b6, b5 and b4 are always read as 1. the status and control bits of the status register are as follows: 6.3.1 wip bit the write in progress (wip) bit indicates whet her the memory is busy with a write or write status register cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. 6.3.2 wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write or write status register instruction is accepted. 6.3.3 bp1, bp0 bits the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against write instructions. these bits are written with the write status register (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits is set to 1, the relevant memory area (as defined in ta bl e 3 ) becomes protected against write (write) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protected mode has not been set. table 5. status register format b7 b0 1 1 1 1 bp1 bp0 wel wip block protect bits write enable latch bit write in progress bit
m95040, m95020, m95010 instructions 19/42 figure 9. read status register (rdsr) sequence c d s 2 1 3456789101112131415 instruction 0 ai01444d q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
instructions m95040, m95020, m95010 20/42 6.4 write status register (wrsr) this instruction has no effect on bits b7, b6, b5, b4, b1 and b0 of the status register. as shown in figure 10 , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte and data byte are then shifted in on serial data input (d). the instruction is terminated by driving chip select (s ) high. chip select (s ) must be driven high after the rising edge of serial clock (c) that latches the eighth bit of the data byte, and before the next rising edge of serial clock (c). if this condition is not met, the write status register (wrsr) instruction is not execut ed. the self-timed write cycle starts, and continues for a period t w (as specified in ta bl e 1 8 to ta bl e 2 2 ), at the end of which the write in progress (wip) bit is reset to 0. the instruction is not accepted, and is not executed, under the following conditions: if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) if a write cycle is already in progress if the device has not been deselected, by chip select (s ) being driven high, after the eighth bit, b0, of the data byte has been latched in if write protect (w ) is low. figure 10. write status register (wrsr) sequence c d ai01445b s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
m95040, m95020, m95010 instructions 21/42 6.5 read from memory array (read) as shown in figure 11 , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte and address byte are then shifted in, on serial data input (d). for the m95040, the most significant address bit, a8, is incorporated as bit b3 of the instruction byte, as shown in ta b l e 4 . the address is loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). if chip select (s ) continues to be driven low, an internal bit-pointer is automatically incremented at each clock cycle, and the corresponding data bit is shifted out. when the highest address is reached, the addr ess counter rolls over to zero, allowing the read cycle to be continued indefinitely. the whole memory can, therefore, be read with a single read instruction. the read cycle is terminated by driving chip select (s ) high. the rising edge of the chip select (s ) signal can occur at any time during the cycle. the first byte addressed can be any byte within any page. the instruction is not accepted, and is not executed, if a write cycle is currently in progress. figure 11. read from memory array (read) sequence 1. depending on the memory size, as shown in table 6 , the most significant address bits are don?t care. table 6. address range bits device m95040 m95020 m95010 address bits a8-a0 a7-a0 a6-a0 c d ai01440e s q a7 2 1 345678910111213141516171819 a6 a5 a4 a3 a2 a1 a0 a8 20 21 22 76543 2 0 1 high impedance data out instruction byte address 0
instructions m95040, m95020, m95010 22/42 6.6 write to memory array (write) as shown in figure 12 , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (d). the instruction is terminated by driving chip select (s ) high after the rising edge of serial clock (c) that latches the last data bit, and before the next rising edge of serial clock (c) occurs anywhere on the bus. in the case of figure 12 , this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. the self-timed write cycle starts, and continues for a period t wc (as specified in ta bl e 1 8 to ta bl e 2 2 ), at the end of which the write in progress (wip) bit is reset to 0. if, though, chip select (s ) continues to be driven low, as shown in figure 13 , the next byte of input data is shifted in. in this way, all the bytes from the given address to the end of the same page can be programmed in a single instruction. if chip select (s ) still continues to be driven low, the next byte of input data is shifted in, and is used to overwrite the byte at the start of the current page. the instruction is not accepted, and is not executed, under the following conditions: if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) if a write cycle is already in progress if the device has not been deselected, by chip select (s ) being driven high, at a byte boundary (after the rising edge of serial clock (c) that latches the last data bit, and before the next rising edge of serial clock (c) occurs anywhere on the bus) if write protect (w ) is low or if the addressed page is in the region protected by the block protect (bp1 and bp0) bits. figure 12. byte write (write) sequence 1. depending on the memory size, as shown in table 6 , the most significant address bits are don?t care. ai01442d c d s q a7 2 1 345678910111213141516171819 a6 a5 a4 a3 a2 a1 a0 a8 20 21 22 23 high impedance instruction byte address 0 765432 0 1 data byte
m95040, m95020, m95010 instructions 23/42 figure 13. page write (write) sequence 1. depending on the memory size, as shown in table 6 , the most significant address bits are don?t care. 6.7 cycling c d s 2 1 345678910111213141516171819 20 21 22 23 instruction byte address 0 data byte 1 c d ai01443d s 26 25 27 28 29 30 31 8+8n 24 data byte 16 9+8n 10+8n 11+8n 12+8n 13+8n 14+8n 15+8n 136 137 138 139 140 141 142 143 data byte n 76 3210 54 data byte 2 7 a7 a6 a5 a4 a3 a2 a1 a0 a8 765432 0 1 7 6543210765432 0 1
power-up and delivery states m95040, m95020, m95010 24/42 7 power-up and delivery states 7.1 power-up state after power-up, the device is in the following state: low power standby power mode deselected (after power-up, a falling ed ge is required on chip select (s ) before any instructions can be started). not in the hold condition the write enable latch (wel) is reset to 0 write in progress (wip) is reset to 0 the bp1 and bp0 bits of the status register are unchanged from the previous power-down (they are non-volatile bits). 7.2 initial delivery state the device is delivered with the memory array set at all 1s (ffh). the block protect (bp1 and bp0) bits are initialized to 0.
m95040, m95020, m95010 maximum rating 25/42 8 maximum rating stressing the device outside the ratings listed in ta bl e 7 may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroe lectronics sure program and other relevant quality documents. table 7. absolute maximum ratings symbol parameter min. max. unit t a ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std- 020c (for small body, sn-pb or pb assembly), the st ecopack? 7191395 specification, and the european directive on re strictions on hazardous substances (rohs) 2002/95/eu. c v o output voltage ?0.50 v cc +0.6 v v i input voltage ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) (2) 2. aec-q100-002 (compliant wi th jedec std jesd22-a114a, c1=100pf, r1=1500 ? , r2=500 ? ) ?4000 4000 v
dc and ac parameters m95040, m95020, m95010 26/42 9 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. 1. output hi-z is defined as the point where data out is no longer driven. figure 14. ac test measurement i/o waveform table 8. operating conditions (m950x0) symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 c table 9. operating conditions (m950x0-w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 c table 10. operating conditions (m950x0-r) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 11. ac test measurement conditions symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing reference voltages 0.3v cc to 0.7v cc v ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
m95040, m95020, m95010 dc and ac parameters 27/42 1. sampled only, not 100% tested, at t a =25c and a frequency of 5mhz. table 12. capacitance symbol parameter test condition min . max . unit c out output capacitance (q) v out = 0v 8 pf c in input capacitance (d) v in = 0v 8 pf input capacitance (other pins) v in = 0v 6 pf table 13. dc characteristics (m950x0, device grade 6) symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1v cc /0.9v cc at 10 mhz, v cc = 5 v, q = open 5ma i cc1 supply current (standby power mode) s = v cc , v cc = 5 v, v in = v ss or v cc 2a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 2 ma, v cc = 5 v 0.4 v v oh output high voltage i oh = ?2 ma, v cc = 5v 0.8v cc v table 14. dc characteristics (m950x0, device grade 3) symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1v cc /0.9v cc at 5 mhz, v cc = 5 v, q = open 3ma i cc1 supply current (standby power mode) s = v cc , v in = v ss or v cc v cc = 5 v 5a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 2 ma, v cc = 5 v 0.4 v v oh output high voltage i oh = ?2 ma, v cc = 5v 0.8v cc v
dc and ac parameters m95040, m95020, m95010 28/42 table 15. dc characteristics (m950x0-w, device grade 6) symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1v cc /0.9v cc at 5 mhz, v cc = 2.5 v, q = open 2ma i cc1 supply current (standby power mode) s = v cc , v in = v ss or v cc v cc = 2.5 v 1a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 1.5 ma, v cc = 2.5 v 0.4 v v oh output high voltage i oh = ?0.4 ma, v cc = 2.5 v 0.8 v cc v table 16. dc characteristics (m950x0-w, device grade 3) symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c = 0.1v cc /0.9v cc at 5 mhz, v cc = 2.5 v, q = open 2ma i cc1 supply current (standby power mode) s = v cc , v in = v ss or v cc v cc = 2.5 v 2a v il input low voltage ?0.45 0.3 v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 1.5 ma, v cc = 2.5 v 0.4 v v oh output high voltage i oh = ?0.4 ma, v cc = 2.5 v 0.8 v cc v table 17. dc characteristics (m950x0-r) symbol parameter test condition min. max. unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current c=0.1v cc /0.9. v cc at 2 mhz, v cc = 1.8 v, q = open 2ma i cc1 supply current (standby power mode) s = v cc , v in = v ss or v cc , v cc = 1.8 v 1a v il input low voltage ?0.45 0.3v cc v v ih input high voltage 0.7 v cc v cc +1 v v ol output low voltage i ol = 0.15 ma, v cc = 1.8 v 0.3 v v oh output high voltage i oh = ?0.1 ma, v cc = 1.8v 0.8v cc v
m95040, m95020, m95010 dc and ac parameters 29/42 table 18. ac characteristics (m950x0, device grade 6) test conditions specified in table 11 and table 8 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 10 mhz t slch t css1 s active setup time 15 ns t shch t css2 s not active setup time 15 ns t shsl t cs s deselect time 40 ns t chsh t csh s active hold time 25 ns t chsl s not active hold time 15 ns t ch (1) 1. t ch + t cl must never be less than the shor test possible clock period, 1 / f c (max) t clh clock high time 40 ns t cl (1) t cll clock low time 40 ns t clch (2) 2. value guaranteed by characterizati on, not 100% tested in production. t rc clock rise time 1 s t chcl (2) t fc clock fall time 1 s t dvch t dsu data in setup time 15 ns t chdx t dh data in hold time 15 ns t hhch clock low hold time after hold not active 15 ns t hlch clock low hold time after hold active 20 ns t clhl clock low setup time before hold active 0 ns t clhh clock low setup time before hold not active 0 ns t shqz (2) t dis output disable time 25 ns t clqv t v clock low to output valid 35 ns t clqx t ho output hold time 0 ns t qlqh (2) t ro output rise time 20 ns t qhql (2) t fo output fall time 20 ns t hhqv t lz hold high to output valid 25 ns t hlqz (2) t hz hold low to output high-z 35 ns t w t wc write time 5 ms
dc and ac parameters m95040, m95020, m95010 30/42 table 19. ac characteristics (m950x0, device grade 3) test conditions specified in table 11 and table 8 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 5 mhz t slch t css1 s active setup time 90 ns t shch t css2 s not active setup time 90 ns t shsl t cs s deselect time 100 ns t chsh t csh s active hold time 90 ns t chsl s not active hold time 90 ns t ch (1) 1. t ch + t cl must never be less than the shor test possible clock period, 1 / f c (max) t clh clock high time 90 ns t cl (1) t cll clock low time 90 ns t clch (2) 2. value guaranteed by characterizati on, not 100% tested in production. t rc clock rise time 1 s t chcl (2) t fc clock fall time 1 s t dvch t dsu data in setup time 20 ns t chdx t dh data in hold time 30 ns t hhch clock low hold time after hold not active 70 ns t hlch clock low hold time after hold active 40 ns t clhl clock low setup time before hold active 0 ns t clhh clock low setup time before hold not active 0 ns t shqz (2) t dis output disable time 100 ns t clqv t v clock low to output valid 60 ns t clqx t ho output hold time 0 ns t qlqh (2) t ro output rise time 50 ns t qhql (2) t fo output fall time 50 ns t hhqv t lz hold high to output valid 50 ns t hlqz (2) t hz hold low to output high-z 100 ns t w t wc write time 5 ms
m95040, m95020, m95010 dc and ac parameters 31/42 table 20. ac characteristics (m950x0-w, device grade 6) test conditions specified in table 11 and table 9 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 5 mhz t slch t css1 s active setup time 90 ns t shch t css2 s not active setup time 90 ns t shsl t cs s deselect time 100 ns t chsh t csh s active hold time 90 ns t chsl s not active hold time 90 ns t ch (1) 1. t ch + t cl must never be less than the shor test possible clock period, 1 / f c (max) t clh clock high time 90 ns t cl (1) t cll clock low time 90 ns t clch (2) 2. value guaranteed by characterizati on, not 100% tested in production. t rc clock rise time 1 s t chcl (2) t fc clock fall time 1 s t dvch t dsu data in setup time 20 ns t chdx t dh data in hold time 30 ns t hhch clock low hold time after hold not active 70 ns t hlch clock low hold time after hold active 40 ns t clhl clock low setup time before hold active 0 ns t clhh clock low setup time before hold not active 0 ns t shqz (2) t dis output disable time 100 ns t clqv t v clock low to output valid 60 ns t clqx t ho output hold time 0 ns t qlqh (2) t ro output rise time 50 ns t qhql (2) t fo output fall time 50 ns t hhqv t lz hold high to output valid 50 ns t hlqz (2) t hz hold low to output high-z 100 ns t w t wc write time 5 ms
dc and ac parameters m95040, m95020, m95010 32/42 table 21. ac characteristics (m950x0-w, device grade 3) test conditions specified in table 11 and table 9 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 5 mhz t slch t css1 s active setup time 90 ns t shch t css2 s not active setup time 90 ns t shsl t cs s deselect time 100 ns t chsh t csh s active hold time 90 ns t chsl s not active hold time 90 ns t ch (1) 1. t ch + t cl must never be less than the shor test possible clock period, 1 / f c (max) t clh clock high time 90 ns t cl (1) t cll clock low time 90 ns t clch (2) 2. value guaranteed by characterizati on, not 100% tested in production. t rc clock rise time 1 s t chcl (2) t fc clock fall time 1 s t dvch t dsu data in setup time 20 ns t chdx t dh data in hold time 30 ns t hhch clock low hold time after hold not active 70 ns t hlch clock low hold time after hold active 40 ns t clhl clock low setup time before hold active 0 ns t clhh clock low set-up time before hold not active 0 ns t shqz (2) t dis output disable time 100 ns t clqv t v clock low to output valid 60 ns t clqx t ho output hold time 0 ns t qlqh (2) t ro output rise time 50 ns t qhql (2) t fo output fall time 50 ns t hhqv t lz hold high to output valid 50 ns t hlqz (2) t hz hold low to output high-z 100 ns t w t wc write time 5 ms
m95040, m95020, m95010 dc and ac parameters 33/42 table 22. ac characteristics (m950x0-r) test conditions specified in table 11 and table 10 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 2 mhz t slch t css1 s active setup time 200 ns t shch t css2 s not active setup time 200 ns t shsl t cs s deselect time 200 ns t chsh t csh s active hold time 200 ns t chsl s not active hold time 200 ns t ch (1) 1. t ch + t cl must never be less than the shor test possible clock period, 1 / f c (max) t clh clock high time 200 ns t cl (1) t cll clock low time 200 ns t clch (2) 2. value guaranteed by characterizati on, not 100% tested in production. t rc clock rise time 1 s t chcl (2) t fc clock fall time 1 s t dvch t dsu data in setup time 40 ns t chdx t dh data in hold time 50 ns t hhch clock low hold time after hold not active 140 ns t hlch clock low hold time after hold active 90 ns t clhl clock low setup time before hold active 0 ns t clhh clock low setup time before hold not active 0 ns t shqz (2) t dis output disable time 250 ns t clqv t v clock low to output valid 180 ns t clqx t ho output hold time 0 ns t qlqh (2) t ro output rise time 100 ns t qhql (2) t fo output fall time 100 ns t hhqv t lz hold high to output valid 100 ns t hlqz (2) t hz hold low to output high-z 250 ns t w t wc write time 10 ms
dc and ac parameters m95040, m95020, m95010 34/42 figure 15. serial input timing figure 16. hold timing c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c q ai01448b s d hold tclhl thlch thhch tclhh thhqv thlqz
m95040, m95020, m95010 dc and ac parameters 35/42 figure 17. output timing c q ai01449e s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv
package mechanical m95040, m95020, m95010 36/42 10 package mechanical figure 18. so8n - 8 lead plastic small outl ine, 150 mils body width, package outline 1. drawing is not to scale. table 23. so8n - 8 lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a1.750.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e1.27? ?0.050? ? h 0.25 0.50 0.010 0.020 k0808 l 0.40 1.27 0.016 0.050 l1 1.04 0.041 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
m95040, m95020, m95010 package mechanical 37/42 figure 19. tssop8 ? 8 lead thin shrink small outline, package outline 1. drawing is not to scale. table 24. tssop8 ? 8 lead thin shrink small outline, package mechanical data symbol millimeters inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0. 0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0. 1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8 n (number of pins) 8 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
package mechanical m95040, m95020, m95010 38/42 figure 20. ufdfpn8 (mlp8) - 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, package outline 1. drawing is not to scale. table 25. ufdfpn8 (mlp8) - 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, package mechanical data symbol millimeters inches typ min max typ min max a 0.55 0.50 0.60 0.022 0.020 0.024 a1 0.00 0.05 0.000 0.002 b 0.25 0.20 0.30 0.010 0.008 0.012 d2.00 0.079 d2 1.55 1.65 0.061 0.065 ddd 0.05 0.002 e3.00 0.118 e2 0.15 0.25 0.006 0.010 e0.50??0.020?? l 0.45 0.40 0.50 0.018 0.016 0.020 l1 0.15 0.006 l3 0.30 0.012 n (number of pins) 8 8 d e ufdfpn-01 a a1 ddd l1 e b d2 l e2 l3
m95040, m95020, m95010 part numbering 39/42 11 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. table 26. ordering information scheme example: m95040 ? w mn 6 t p /w device type m95 = spi serial access eeprom device function 040 = 4 kbit (512 x 8) 020 = 2 kbit (256 x 8) 010 = 1 kbit (128 x 8) operating voltage blank = v cc = 4.5 to 5.5v w = v cc = 2.5 to 5.5v r = v cc = 1.8 to 5.5v package mn = so8 (150 mil width) dw = tssop8 (169 mil width) mb = ufdfpn8 (mlp8) 2 3mm device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow 3 = device tested with high reliability certified flow (1) . automotive temperature range (?40 to 125 c) 1. st strongly recommends the use of the automotive grade devices for use in an automotive environment. the high reliability certified flow (hrcf) is des cribed in the quality note qnee9801. please ask your nearest st sales office for a copy. option blank = standard packing t = tape and reel packing plating technology blank = standard snpb plating p or g = ecopack? (rohs compliant) process (2) 2. used only for device grade 3 /w, /g or /s = f6sp36%
revision history m95040, m95020, m95010 40/42 12 revision history table 27. document revision history date version changes 10-may-2000 2.2 s/issuing three bytes/issuing two byte s/ in the 2nd sentence of the byte write operation 16-mar-2001 2.3 human body model meets jedec std (table 2). minor adjustments to figs 7,9,10,11 & tab 9. wording changes, according to the standard glossary illustrations and package mechanical data updated 19-jul-2001 2.4 temperature range ?3? added to the -w supply voltage range in dc and ac characteristics 11-oct-2001 3.0 document reformatted using the new template 26-feb-2002 3.1 description of chip deselect after 8th clock pulse made more explicit 27-sep-2002 3.2 position of a8 in read instruction sequence figure corrected. load capacitance c l changed 24-oct-2002 3.3 minimum values for tchhl and tchhh changed. 24-feb-2003 3.4 description of read from memory array (read) instruction corrected, and clarified 28-may-2003 3.5 new products, identified by the process letter w, added 25-jun-2003 3.6 correction to current products, identif ied by the process letter k not l. i cc changed in dc characteristics, and t chhl , t chhh substituted in ac characteristics voltage range -s upgraded by removing it, and adding the -r voltage range in its place temperature range 5 removed. 21-nov-2003 4.0 table of content s, and pb-free options added. v il (min) improved to -0.45v 02-feb-2004 4.1 v il (max) and t clqv (max) changed 01-mar-2004 5.0 absolute maximum ratings for v io (min) and v cc (min) improved. soldering temperature information clarified for rohs compliant devices. new 5v and 2.5v devices, with process letter w, promoted from preliminary data to full data. device grade 3 clarified, with reference to hrcf and automotive environments
m95040, m95020, m95010 revision history 41/42 05-oct-2004 6.0 product list summary table added. process identification letter ?g? information added. order information for tape and reel changed to t. aec-q100-002 compliance. device grade information clarified. thhqx corrected to thhqv. signal description updated. 10mhz, 5ms write is now the present product. tch+tcl<1/fc constraint clarified 06-nov-2006 7 document converted to new template, table 5: status register format moved to below section 6.3: read status register (rdsr) . pdip package removed. ufdfpn8 (mb) package added (see figure 20 and ta bl e 2 5 ) and so8n package specifications updated (see figure 18 and ta bl e 2 3 ). packages are ecopack? compliant. section 6.7: cycling added. section 2.8: supply voltage (v cc ) added and information removed below section 4: operating features . figure 3: bus master and memory devices on the spi bus modified. t lead parameter modified, note 1 changed, and t a added to ta b l e 7 : absolute maximum ratings . characteristics of previous product iden tified by process letter k removed. cl modified in table 11: ac test measurement conditions . note removed below ta bl e 1 3 and ta bl e 1 4 . information in ta bl e 1 7 is no longer preliminary data, i cc , i cc1 and v il modified. end timing line of t shqz moved in figure 17 . t chhl and t chhh changed to t clhl and t clhh , respectively in figure 16 , ta b l e 1 8 , ta b l e 1 9 , ta bl e 2 0 , ta bl e 2 1 and ta bl e 2 2 . plating technology and process updated in table 26: ordering information scheme . table 27. document revision history (continued) date version changes
m95040, m95020, m95010 42/42 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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